Senior / Lead ASIC DSP Engineer for pre-IPO world-wide IC leader - CyberCoders (Mission Viejo, CA)
What's in it for you:
- Well-Funded, Exciting, and Growing Start-Up - Tremendous opportunity for career growth - Competitive compensation that includes Pre-IPO Stock - Great benefits package with possible sign-on and performance bonus - Opportunity to work in Northern or Southern California What you need for this position:
- BSEE (MSEE Preferred) and 7
years of ASIC Design Experience - Expertise or strong background in DSP - Outstanding hands on experience with Verilog, VHDL and/or SystemVerilog.
Hands on experience with C/C++, SystemC and/or Matlab a plus - Hands on RTL Design, Debug, verification - Strong hands on STA, Synthesis, DFT, LEC, Formal Verification, BIST, JTag, etc.
- Synopsis Design Compiler, Formality & Primetime, and/or Cadence RTL Compiler experience - Scripting experience with Perl, tcl or other - Low-power Design/Verification flow is a plus What you'll be doing:
- Optical DSP block RTL design, modeling, verification, STA, formal verification - Hands on coding of DSP blocks, Verification Plans & Execution, RTL Coding, etc.
- DSP, Optical Networking, other chip development - Technical leadership So, if you are an ASIC Design Engineer with outstanding hands on DSP experience, please apply today! Source:
.
Estimated Salary: $20 to $28 per hour based on qualifications.
- Well-Funded, Exciting, and Growing Start-Up - Tremendous opportunity for career growth - Competitive compensation that includes Pre-IPO Stock - Great benefits package with possible sign-on and performance bonus - Opportunity to work in Northern or Southern California What you need for this position:
- BSEE (MSEE Preferred) and 7
years of ASIC Design Experience - Expertise or strong background in DSP - Outstanding hands on experience with Verilog, VHDL and/or SystemVerilog.
Hands on experience with C/C++, SystemC and/or Matlab a plus - Hands on RTL Design, Debug, verification - Strong hands on STA, Synthesis, DFT, LEC, Formal Verification, BIST, JTag, etc.
- Synopsis Design Compiler, Formality & Primetime, and/or Cadence RTL Compiler experience - Scripting experience with Perl, tcl or other - Low-power Design/Verification flow is a plus What you'll be doing:
- Optical DSP block RTL design, modeling, verification, STA, formal verification - Hands on coding of DSP blocks, Verification Plans & Execution, RTL Coding, etc.
- DSP, Optical Networking, other chip development - Technical leadership So, if you are an ASIC Design Engineer with outstanding hands on DSP experience, please apply today! Source:
.
Estimated Salary: $20 to $28 per hour based on qualifications.
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