Sr. ASIC/SOC DFT Engineer (Silicon Engineering)
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not.
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR.
ASIC/SOC DFT ENGINEER (SILICON ENGINEERING)At SpaceX we re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world s most advanced broadband internet system.
Starlink is the world s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide.
We design, build, test, and operate all parts of the system thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together.
We ve only begun to scratch the surface of Starlink s potential global impact and are looking for best-in-class engineers to help maximize Starlink s utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation).
In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe.
These chips are enabling connectivity in places it has previously not been available, affordable or reliable.
Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
Responsibilities:
Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) toolsIntegration and verification of Design for Test (DFT) fabrics and IP within SubsystemsRunning and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverageRun ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goalsRun and debug non-timing and SDF annotated gate level simulationsCreating ATPG content for use in post-silicon testing and validating that content through gate level simulationCollaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in siliconBASIC
Qualifications:
Bachelor s degree in electrical engineering, computer engineering or computer science5
years of professional experience working with ASICs of FPGAsExperience in scan insertion or DFT setup, integration and validationPREFERRED SKILLS AND
Experience:
Understanding of ASIC design flow, methodologies, physical design, and verificationRTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFTAbility to solve complex problems including clock domain crossings and power optimizationExperience with UPF (unified power format), formal verification, and DRC rule checking experienceFamiliar with advanced silicon process and technology nodes for high speed and low power consumptionExperience with high reliability design and implementationsExcellent scripting skills (csh/bash, Perl, Python etc.
)Familiar with implementation or integration of design blocks using Verilog/SystemVerilogAbility to work in a dynamic environment with changing needs and requirementsTeam-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basisEnjoys being challenged and learning new skillsADDITIONAL REQUIREMENTS:
Must be willing to work extended hours and weekends as needed COMPENSATION &
Benefits:
Pay range:
DFT Engineer/Senior:
$160,000.
00 - $220,000/per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations:
job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX.
You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks.
You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year.
Exempt employees are eligible for 5 days of sick leave per year.
ITAR REQUIREMENTS:
To conform to U.
S.
Government export regulations, applicant must be a (i) U.
S.
citizen or national, (ii) U.
S.
lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.
S.
C.
1157, or (iv) Asylee under 8 U.
S.
C.
1158, or be eligible to obtain the required authorizations from the U.
S.
Department of State.
Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.
.
Estimated Salary: $20 to $28 per hour based on qualifications.
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR.
ASIC/SOC DFT ENGINEER (SILICON ENGINEERING)At SpaceX we re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world s most advanced broadband internet system.
Starlink is the world s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide.
We design, build, test, and operate all parts of the system thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together.
We ve only begun to scratch the surface of Starlink s potential global impact and are looking for best-in-class engineers to help maximize Starlink s utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation).
In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe.
These chips are enabling connectivity in places it has previously not been available, affordable or reliable.
Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
Responsibilities:
Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) toolsIntegration and verification of Design for Test (DFT) fabrics and IP within SubsystemsRunning and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverageRun ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goalsRun and debug non-timing and SDF annotated gate level simulationsCreating ATPG content for use in post-silicon testing and validating that content through gate level simulationCollaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in siliconBASIC
Qualifications:
Bachelor s degree in electrical engineering, computer engineering or computer science5
years of professional experience working with ASICs of FPGAsExperience in scan insertion or DFT setup, integration and validationPREFERRED SKILLS AND
Experience:
Understanding of ASIC design flow, methodologies, physical design, and verificationRTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFTAbility to solve complex problems including clock domain crossings and power optimizationExperience with UPF (unified power format), formal verification, and DRC rule checking experienceFamiliar with advanced silicon process and technology nodes for high speed and low power consumptionExperience with high reliability design and implementationsExcellent scripting skills (csh/bash, Perl, Python etc.
)Familiar with implementation or integration of design blocks using Verilog/SystemVerilogAbility to work in a dynamic environment with changing needs and requirementsTeam-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basisEnjoys being challenged and learning new skillsADDITIONAL REQUIREMENTS:
Must be willing to work extended hours and weekends as needed COMPENSATION &
Benefits:
Pay range:
DFT Engineer/Senior:
$160,000.
00 - $220,000/per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations:
job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX.
You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks.
You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year.
Exempt employees are eligible for 5 days of sick leave per year.
ITAR REQUIREMENTS:
To conform to U.
S.
Government export regulations, applicant must be a (i) U.
S.
citizen or national, (ii) U.
S.
lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.
S.
C.
1157, or (iv) Asylee under 8 U.
S.
C.
1158, or be eligible to obtain the required authorizations from the U.
S.
Department of State.
Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.
.
Estimated Salary: $20 to $28 per hour based on qualifications.
|
|
 | |
